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the m pd17p068 is a one-time prom version of the m pd17068 that has on-chip mask rom. the m pd17p068, which can be programmed only once, is suited for testing during development of m pd17068 systems and limited production runs. use this data sheet together with m pd17068 documents. the m pd17p068 does not provide a level of reliability intended for mass production of the customer's products. use it only for functional evaluation when experimenting or doing product trial tests. features ? compatible with the m pd17068 ? one-time prom : 12160 16 bits ? operating voltage : v dd = 5 v 10 % ordering information part number package m pd17p068gf-3ba 100-pin plastic qfp (14 20mm) m pd17p068 mos integrated circuit 4-bit single-chip microcontroller with on-chip hardware for tv systems the information in this document is subject to change without notice. document no. u10336ej1v0ds00 date published november 1995 p printed in japan 1995 data sheet
2 m pd17p068 idc (image display controller) data memory (ram) functional outline part number m pd17068 m pd17p068 item mask rom one-time prom program memory (rom) ? 12160 16 bits table reference area: 12160 16 bits character rom (crom) ? 6144 16 bits ? 1007 4 bits (including area serving also as vram) data buffer: 4 4 bits, general register: 16 4 bits video ram (vram) ? 672 4 bits (also used as data memory (ram)) system register ? 12 4 bits register file ? 12 4 bits general port register ? 12 4 bits instruction execution time ? 2 m s (when using 8-mhz crystal resonator) stack levels ? 12 levels (stack manipulation possible) ? i/o ports : 19 general ports ? input ports : 4 ? output ports : 21 ? number of displayable characters : 192 characters max. per screen (up to 350 characters with program) ? display format : 16 16-dot mode 15 lines 24 columns : 14 16-dot mode 17 lines 24 columns ? character types : 255 types (user programmable) ? character format : 16 16 dots and 14 16 dots selectable (2 dots can be placed between characters) ? color : 15 colors ? character size : vertical : 16 sizes (specifiable for each line) horizontal : 24 sizes (specifiable for each character) ? 2 systems serial interface serial interface 0 (compatible with 2-wire system, 3-wire system and i 2 c bus) serial interface 1 (3-wire system) d/a converter ? 8 bits 9 channels (pwm output, 12.5 v max.) a/d converter ? 6 bits 8 channels (successive approximation by software) ? 10 channels (maskable interrupt) interrupt external interrupt : 3 channels (int 0 , int nc , v sync , h sync ) internal interrupt : 7 channels (timer 0, 1, serial interface 0, 1, basic timer 2, vram pointer, timer 0 overflow)
3 m pd17p068 part number m pd17068 m pd17p068 item timer 0 : 10 m s to 204.75 ms (interrupt) timer 1 : 1 m s to 256 ms (interrupt) basic timer 0 : 1, 5, 100 ms (carry) basic timer 1 : 125 m s, 1 ms, 5 ms, 100 ms, external (carry) basic timer 2 : 125 m s, 1 ms, 5 ms, 100 ms, external (interrupt) watch timer : date, hour, minute, second (counter) ? power-on reset reset ? reset with ce pin (ce pin: low level ? high level) ? power interruption detection supply voltage v dd = 5 v 10 % package 100-pin plastic qfp (14 20 mm) timer
4 m pd17p068 block diagram ram 1007 4 bits vram (672 4 bits) system reg. rf instruction decoder one-time prom 12160 16 bits crom 6144 16 bits program counter stack 12 14 bits alu a/d converter d/a converter osc watch timer timer0 timer1 basic timer0 basic timer1 basic timer2 serial i/o0 serial i/o1 interrupt adc 0 adc 1 (p0d 0 /md 0 /xt out ) adc 2 (p0d 1 /md 1 /xt in ) adc 3 (p0d 2 /md 2 ) adc 4 (p0d 3 /md 3 ) adc 5 (p1c 0 /d 0 ) adc 7 (p1c 2 /d 2 ) pwm 0 (p2c 0 ) pwm 3 (p2c 3 ) pwm 4 (p2b 0 ) pwm 7 (p2b 3 ) pwm 8 (p2a 0 ) xt in (p0d 1 /adc 2 ) xt out (p0d 0 /adc 1 ) ckout (p1b 1 ) tmin (p1b 3 ) sda (p0a 0 ) scl (p0a 1 ) sck 0 (p0a 2 ) so 0 (p0a 3 ) si 0 (p0b 0 ) si 1 (p2d 2 ) sck 1 (p2d 0 ) so 1 (p2d 1 ) int nc (v pp ) int 0 pll osc circuit idc hsync counter port main oscillator reset 3 4 4 4 4 4 4 4 4 4 4 vco psc eo osc in osc out h sync v sync red green blue blank i (p0b 2 ) hscnt (p0b 3 ) p0a 0 -p0a 3 p0b 0 -p0b 3 p0c 0 -p0c 3 p0d 0 -p0d 3 p1a 0 -p1a 3 p1b 0 -p1b 3 p1c 0 -p1c 3 p1d 0 -p1d 3 p2a 0 p2b 0 -p2b 3 p2c 0- p2c 3 p2d 0 -p2d 2 x in /clk x out v dd ce rls stp /p1b 2 gnd 0 , gnd 1 cpu peripheral (d 4 -d 7 )
5 m pd17p068 pin configuration (top view) (1) normal operation mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 p0d 2 /adc 3 p0d 3 /adc 4 p1c 0 /adc 5 p1c 1 /adc 6 nc p1c 2 /adc 7 p1c 3 nc adc 0 nc p0c 0 nc p0c 1 nc p0c 2 nc p0c 3 nc p2c 0 /pwm 0 nc p2c 1 /pwm 1 nc p2c 2 /pwm 2 nc p2c 3 /pwm 3 nc p2b 0 /pwm 4 p2b 1 /pwm 5 p2b 2 /pwm 6 p2b 3 /pwm 7 p1d 2 p1d 1 p1d 0 int 0 nc p1b 3 /tmin p1b 2 /rls stp nc p1b 1 /ckout p1b 0 nc nc p1a 3 p1a 2 nc nc nc p1a 1 p1a 0 nc p2a 0 /pwm 8 nc nc p2d 2 /si 1 p2d 1 /so 1 p2d 0 /sck 1 nc gnd 0 osc out osc in red green nc blue blank h sync nc v sync p0b 3 /hscnt nc nc p0b 2 /i nc p0b 1 p0b 0 /si 0 p0a 3 /so 0 p0a 2 /sck 0 nc p0a 1 /scl p0a 0 /sda p1d 3 ce psc eo gnd 2 gnd 1 nc nc nc nc nc v dd1 nc v dd0 x out int nc xt out /adc 1 /p0d 0 xt in /adc 2 /p0d 1 x in vco pd17p068gf-3ba m
6 m pd17p068 (2) prom programming mode caution contents in parentheses indicate how to handle unused pins in prom programming mode. l: connect to gnd via a resistor (470 w ) separately. open: leave unconnected. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 md 2 md 3 d 0 d 1 (open) d 2 d 3 (open) (open) (l) (open) d 7 d 6 (open) d 5 d 4 (open) (l) (open) gnd 0 (open) (l) (open) (open) (open) (open) (open) gnd 2 gnd 1 (open) v dd1 v dd0 (open) v pp md 0 md 1 clk (l) pd17p068gf-3ba (open) (open) m (l) (l) (l) (l) (l) (l)
7 m pd17p068 pin identifications adc 0 -adc 7 : a/d converter input p1c 0 -p1c 3 : port 1c blank : blanking signal output p1d 0 -p1d 3 : port 1d blue : character signal output p2a 0 : port 2a ce : chip enable p2b 0 -p2b 3 : port 2b ckout : watch timer adjustment p2c 0 -p2c 3 : port 2c output p2d 0 -p2d 2 : port 2d clk : address update clock input psc : pulse swallow control output d 0 -d 7 : data input/output pwm 0 -pwm 8 : pulse-width modulation output eo : error out red : character signal output gnd 0 -gnd 2 : ground rls stp : clock stop release signal input green : character signal output sck 0 , sck 1 : shift clock input/output hscnt : horizontal synchronizing scl : shift clock input/output signal counter input sda : serial data input/output h sync : horizontal synchronizing sl 0 , sl 1 : serial data input signal input so 0 , so 1: serial data output i : character signal output tmin : event input of basic timer 1 or 2 int 0 , int nc : external interrupt request vco : local oscillation input signal input v dd0 , v dd1 : positive power supply md 0 -md 3 : operation mode select v pp : program voltage application nc : no connection v sync : vertical synchronizing signal input osc in , osc out : lc oscillation for idc x in , x out : main clock oscillation p0a 0 -p0a 3 : port 0a xt in , xt out : watch timer oscillation p0b 0 -p0b 3 : port 0b p0c 0 -p0c 3 : port 0c p0d 0 -p0d 3 : port 0d p1a 0 -p1a 3 : port 1a p1b 0 -p1b 3 : port 1b
8 m pd17p068 contents 1. pin functions ............................................................................................................................... .. 9 1.1 normal operation mode ........................................................................................................................... 9 1.2 prom programming mode .................................................................................................................... 13 1.3 pin equivalent circuits .......................................................................................................................... 14 1.4 handling of unused pins ....................................................................................................................... 19 1.5 notes on using the ce and int nc pins (only in normal operation mode) ................................... 21 2. write, read, and verify of one-time prom (program memory) ............................ 22 2.1 operation modes in program memory write/read/verify ................................................................. 23 2.2 prom write procedure .......................................................................................................................... 24 2.3 prom read procedure .......................................................................................................................... 25 3. electrical specifications .................................................................................................... 26 4. package drawing ...................................................................................................................... 31 appendix development tools .................................................................................................... 32
9 m pd17p068 1. pin functions 1.1 normal operation mode (1) port pins pin name description i/o output type when reset shared by 4-bit i/o port. these pins serve as a bit-selectable n-ch open drain 4-bit input/output port. all these pins are set to input pins when power (v dd ) i/o input is turned on, when clock is stopped, or when reset signal is input to the ce pin. 4-bit i/o port. these pins serve as a bit-selectable 4-bit input/output port. all these pins are set to input pins when power (v dd ) is turned on, when clock is stopped, or when reset signal is input to the ce pin. these pins serve as a 4-bit output port. the output state of each pin is undefined o cmos push-pull undefined output after power (v dd ) is turned on. these pins serve as a 4-bit input port. i input with pull- down resistor n-ch open-drain these pins serve as a 4-bit output port. o middle voltage, undefined output high current 4-bit i/o port. these pins serve as a bit-selectable 4-bit i/o cmos push-pull input input/output port. 4-bit i/o port. these pins serve as 4-bit- i/o cmos push-pull input selectable 4-bit i/o port. these pins serve as a 4-bit output port. o cmos push-pull undefined output n-ch open-drain this pin serves as a 1-bit output port. o undefined output middle voltage n-ch open-drain these pins serve as a 4-bit output port. o undefined output middle voltage n-ch open-drain these pins serve as a 4-bit output port. o undefined output middle voltage these pins serve as a bit-selectable 3-bit input/output port. all these pins are set to input pins when power (v dd ) is turned on, i/o cmos push-pull input when clock is stopped, or when reset signal is input to the ce pin. p0a 0 sda p0a 1 scl p0a 2 sck 0 p0a 3 so 0 p0b 0 sl 0 p0b 1 p0b 2 l p0b 3 hscnt p0c 0 ? p0c 3 p0d 0 adc 1 /xt out p0d 1 adc 2 /xt in p0d 2 adc 3 p0d 3 adc 4 p1a 0 ? p1a 3 p1b 0 p1b 1 ckout p1b 2 rls stp p1b 3 tmin p1c 0 adc 5 ? ? p1c 2 adc 7 p1c 3 p1d 0 ? p1d 3 p2a 0 pwm 8 p2b 0 pwm 4 ? ? p2b 3 pwm 7 p2c 0 pwm 0 ? ? p2c 3 pwm 3 p2d 0 sck 1 p2d 1 so 1 p2d 2 sl 1 cmos push-pull i/o cmos push-pull input
10 m pd17p068 (2) non-port pins pin name description i/o output type when reset shared by this pin outputs signals from the charge pump of the pll frequency synthesizer. if the frequency divided from the local eo oscillator (vco) frequency is higher (lower) o cmos 3-state high-impedance than the reference frequency, high (low) level is output from this pin, respectively. when the two frequencies match, this pin is placed in the high-impedance state. this pin outputs pulse swallow control psc signal. this signal switches division ratio o cmos push-pull output for the dedicated prescaler m pb595. this pin is the input of the local oscillator. the output signal coming from the local oscillator (vco) in the tuner and divided by vco the dedicated prescaler m pb595 should be i input to this pin, where the m pb595 is a two-module prescaler capable of frequency division up to 1 ghz. this pin is the input of the h sync signal hscnt i input p0b 3 counter. this active-high pin outputs blanking blank o cmos push-pull low level output signals to delete video signals. this active-high pin outputs character red data that correspond the r signal (one of o cmos push-pull low level output the rgb signals of idc). this active-high pin outputs character data green that correspond the g signal (one of the o cmos push-pull low level output rgb signals of idc). this active-high pin outputs character data blue that correspond the b signal (one of the o cmos push-pull low level output rgb signals of idc). this pin outputs character data that i o cmos push-pull input p0b 2 correspond the i signal of idc. the h sync signals for idc should be h sync i input input to this pin in an active-low manner. the v sync signals for idc should be input v sync i input to this pin in an active-low manner. these are the input and output pins of the lc oscillation circuit for idc. adjust the oscillation frequency to 10 mhz. these are the analog input pins of the i input 6-bit resolution a/d converter. these are the analog input pins of the i input 6-bit resolution a/d converter. p0d 0 /xt out p0d 1 /xt in p0d 2 p0d 3 p1c 0 ? p1c 2 osc in osc out adc 0 adc 1 adc 2 adc 3 adc 4 adc 5 ? adc 7 internally pulled down
11 m pd17p068 pin name description i/o output type when reset shared by pwm 0 p2c 0 ? ? pwm 3 p2c 3 pwm 4 these are the output pins of the o n-ch open-drain p2b 0 ? 8-bit resolution d/a converter. middle-voltage ? pwm 7 p2b 3 pwm 8 p2a 0 tmin this pin is the input of basic timer 1 or 2. i input p1b 3 a 32.768-khz crystal resonator for watch timer operation should be connected to these pins. this pin outputs the signal to control the ckout o cmos push-pull input p1b 1 watch timer. sck 0 p0a 2 these pins input and output shift clocks. i/o cmos push-pull input sck 1 p2d 0 sl 0 p0b 0 these pins input serial data. i input sl 1 p2d 2 so 0 p0a 3 these pins output serial data. o cmos push-pull input so 1 p2d 1 scl these pins input and output shift clocks. i/o n-ch open-drain input p0a 1 sda these pins input and output serial data. i/o n-ch open-drain input p0a 0 this pin inputs interrupt request signal from external device. an interrupt int 0 request is issued at the rising or falling i input edge of the input signal applied to this pin. this pin inputs interrupt request signal with noise canceller. using this pin to input signals with noise such as int nc commands from a remote control unit i input simplifies programming processes. the interrupt request issuing timing is programmable to either rising or falling edge of the input signal to this pin. xt in xt out p0d 1 /adc 2 p0d 0 /adc 1 low-level output or high impe- dance
12 m pd17p068 pin name description i/o output type when reset shared by this pin selects a device to be activated, or resets this device. (1) use as input of device selection signal when ce=high, pll synthesizer and idc operate. when ce=low, their ce operation are disabled (stops). i input (2) use as reset input when ce changes from low to high, this device is reset in synchronization with the carry ff operation for the internal basic interval timer 0. this pin inputs the clock stop release rls stp i input p1b 2 signal. an 8-mhz crystal resonator for main clock generation should be connected to these pins. these pins supply positive power voltage for this device. the power supply voltage of 5 v 10 % should be applied to these v dd0 pins when all functions operate. when idc is disabled, the voltage range from 4.0 to 5.5 v is allowed. when clock is stopped, the applied voltage to these pins may be lowered down to 2.5 v. because this device internally has the power-on reset circuit, the voltages applied to these pins are changed from 0 to 4.0 v, v dd1 system reset sequence is started and the program is implemented from address 0h. to assure normal operations of the power-on reset circuit, the rise time from 0 to 4.0 v should be shorter than 500 ms. these pins supply the ground level for this device. nc this pin should be left unconnected. x in x out gnd 0 ? gnd 2
13 m pd17p068 1.2 prom programming mode pin name description i/o output type d 0 8-bit data input/output pins used in ? program memory write, read, verify i/o cmos push-pull d 7 modes. md 0 input pins that select an operation mode ? in program memory write, read, verify i md 3 modes. clock input for address update in program clk i memory write, read, verify modes. programming voltage (+12.5 v) application v pp pin in program memory write, read, verify modes. positive power supply. +5 v should be applied to these pins in program memory write, read, verify modes. gnd 0 ? ground pin gnd 2 remark the other pins are not used in the prom programming mode. how to handle the other pins are described in the section "pin configuration (2) prom programming mode" . v dd0 v dd1
14 m pd17p068 1.3 pin equivalent circuits (1) p0a (p0a 3 /so 0 , p0a 2 /sck 0 ) p0b (p0b 2 /l, p0b 1 , p0b 0 /sl 0 ) p1b (p1b 2 /rls stp , p1b 1 /ckout, p1b 0 ) p1c (p1c 3 , p1c 2 /adc 7 , p1c 1 /adc 6 , p1c 0 /adc 5 ) (input/output) (2) p2d (p2d 2 /sl 1 , p2d 1 /so 1 , p2d 0 /sck 1 ) : (input/output) v dd v dd reset (other than p1c) read instruction (p1c only) a/d converter (p1c/adc only) v dd v dd reset
15 m pd17p068 (3) p0a (p0a 1 /scl, p0a 0 /sda) : (input/output) (4) p0c (p0c 3 , p0c 2 , p0c 1 , p0c 0 ) p1d (p1d 3 , p1d 2 , p1d 1 , p1d 0 ) red, green, blue, blank psc (5) p1a (p1a 3 , p1a 2 , p1a 1 , p1a 0 ) p2a (p2a 0 /pwm 8 ) p2b (p2b 3 /pwm 7 , p2b 2 /pwm 6 , p2b 1 /pwm 5 , p2b 0 /pwm 4 ) p2c (p2c 3 /pwm 3 , p2c 2 /pwm 2 , p2c 1 /pwm 1 , p2c 0 /pwm 0 ) (6) p0d (p0d 3 /adc 4 , p0d 2 /adc 3 , p0d 1 /adc 2 /xt in , p0d 0 /adc 1 /xt out ) : (input) (output) (output) v dd v dd v dd high on-resistance
16 m pd17p068 (7) adc 0 : (input) (8) p0b 3 /hscnt : (input/output) v dd v dd v dd reset v dd v dd port h sync signal counter
17 m pd17p068 (9) p1b 3 /tmin : (input/output) (10) h sync , v sync , ce, int 0 , int nc : (schmitt triggered input) v dd v dd reset v dd v dd port timer counter v dd
18 m pd17p068 (11) x in , osc in : x out , osc out : (12) eo : (output) (13) vco : (input) v dd v dd x in , osc in x out , osc out high on-resistance v dd v dd v dd (input)
19 m pd17p068 1.4 handling of unused pins the following are recommended for handling unused pins. table 1-1. handling of unused pins (1/2) (a) port pins pin name input/output circuit type recommended handling when in unused state p0a 0 /sda input/output note 1 specify a general-purpose input port by software and connect each pin p0a 1 /scl to v dd or gnd through a resistor. note 2 p0a 2 /sck 0 p0a 3 /so 0 p0b 0 /si 0 p0b 1 p0b 2 /i p0b 3 /hscnt p0c 0 -p0c 3 cmos push-pull output open p0d 0 /adc 1 /xt out input individually connect to gnd through a resistor. note 2 p0d 1 /adc 2 /xt in p0d 2 /adc 3 , p0d 3 /adc 4 p1a 0 -p1a 3 n-ch open-drain output specify low-level output by software, then open. p1b 0 input/output note 1 specify a general-purpose input port by software and connect each pin p1b 1 /ckout to v dd or gnd through a resistor. note 2 p1b 2 /rls stp p1b 3 /tmin p1c 0 /adc 5 -p1c 2 /adc 7 p1c 3 p1d 0 -p1d 3 cmos push-pull output open p2a 0 /pwm 8 n-ch open-drain output specify low-level output by software, then open. p2b 0 /pwm 4 -p2b 3 /pwm 7 p2c 0 /pwm 0 -p2c 3 /pwm 3 p2d 0 /sck 1 input/output note 1 specify a general-purpose input port by software and connect each pin p2d 1 /so 1 to v dd or gnd through a resistor. note 2 p2d 2 /si 1 notes 1. input ports go to input mode when the power supply rises, when the clock stops, and on ce reset. 2. be careful of the fact that when an external pull-up (connection to v dd through a resistor) or pull-down (connection gnd through a resistor) is made, if the pull-up or pull-down is done through a resistor with a high value, because the pin comes near to being in high impedance, the consumed (through) current increases. this also depends on the application circuit, but a typical value for a pull-up or pull-down resistor is a few tens of k w .
20 m pd17p068 table 1-1. handling of unused pins (2/2) (b) pins other than ports pin name input/output circuit type recommended handling when in unused state adc 0 input connect to v dd or gnd through a resistor. note blank output open blue output open ce input connect to v dd through a resistor. note eo output open green output open h sync input connect to v dd or gnd through a resistor. note int 0 input connect to v dd or gnd through a resistor. note int nc input connect to v dd or gnd through a resistor. note osc in input connect to v dd through a resistor. note osc out output open psc output open red output open vco input with pull-down resistor open v sync input connect to v dd or gnd through a resistor. note note be careful of the fact that when an external pull-up (connection to v dd through a resistor) or pull-down (connection gnd through a resistor) is made, if the pull-up or pull-down is done through a resistor with a high value, because the pin comes near to being in high impedance, the consumed (through) current increases. this also depends on the application circuit, but a typical value for a pull-up or pull-down resistor is a few tens of k w .
21 m pd17p068 1.5 notes on using the ce and int nc pins (only in normal operation mode) in addition to the functions shown in 1.1 normal operation mode , the ce pin also has the function of setting a test mode (for ic testing) in which the internal operations of the m pd17p068 are tested. also, the int nc pin has the function of the v pp pin for program memory write/verify. when a voltage higher than v dd is applied to either of these pins, the test or program memory write/verify mode is set. this means that, even during normal operation, the m pd17p068 may be set in the test mode if noise exceeding v dd is applied. for example, if the wiring length of the ce or int nc pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. connect diode with low v f between v dd connect capacitor between v dd and ce/int nc pin and ce/int nc pin v dd ce, int nc v dd v dd diode with low v f ce, int nc v dd
22 m pd17p068 2. write, read, and verify of one-time prom (program memory) the program memory contained in the m pd17p068 is the 12160 16-bit one-time prom that can electrically be written one time only. this prom is accessed in 16 bits per word in normal operation mode, and in 8 bits per word in write, read, verify modes. the 16 bits of a word in normal mode are divided into higher 8 bits and lower 8 bits which are assigned to even and odd addresses, respectively. when the prom is written, read, or verified, set this device into the prom mode. in this mode, these pins are used as shown in the table below. notice that no address input pins are provided. addresses are automatically updated by the clock signal supplied from the clk pin. table 2-1. pins used in program memory write, read, and verify modes pin function v pp programming voltage (+12.5 v) application clk address update clock input md 0 -md 3 operation mode selection d 0 -d 7 8-bit data input/output v dd0 , v dd1 power supply voltage (+5 v) application to write the internal prom, use the nec-specified prom programming equipment (prom programmer) and program adapter as listed below. prom programmer af-9703 (ando electric corporation) af-9704 (ando electric corporation) af-9705 (ando electric corporation) af-9706 (ando electric corporation) program adapter af-9808l (ando electric corporation) remark for details on these prom programmer and program adapter, consult with ando electric corporation (03-3733-1151 tokyo, japan).
23 m pd17p068 2.1 operation modes in program memory write/read/verify when +5 v is applied to the v dd pin and +12.5 v is applied to the v pp pin, this device enters the program memory write/read/verify modes. operation mode is determined by the setting of md 0 to md 3 pins as indicated in the table below. all input pins irrelevant to the program memory write/read/verify operation should be left unconnected or connected to gnd via a pull-down resistor of 470 w (refer to the section "pin configuration (2) prom programming mode). " table 2-2. operation modes in program memory write/read/verify pin states operation mode v pp v dd md 0 md 1 md 2 md 3 h l h l program memory address 0 clear l h h h write l l h h read, verify h x h h program inhibit remark x: l or h +12.5 v +5 v
24 m pd17p068 2.2 prom write procedure data can be written to the prom in high speeds by using the following procedures. (1) set the pins not used for programming as indicated in section "pin configuration (2) prom programming mode." set the clk pin to low level. (2) supply +5 v to the v dd and v pp pins. (3) provide a 10- m s wait state. (4) program memory address 0 clear mode is entered. (5) supply +6 v to the v dd pin, and +12.5 v to the v pp pin. (6) program inhibit mode is entered. (7) provide write data for 1 ms in write mode. (8) program inhibit mode is entered. (9) use the verify mode to test data. if the data has been written, proceed to (10). if not, repeat steps (7) to (9). (10) provide write data (for additional writing) for 1 ms times the number of repeats performed between steps (7) to (9). (11) program inhibit mode is entered. (12) provide four pulses to the clk pin to increment the address. (13) repeat steps (7) to (12) until the last address is reached. (14) program memory address 0 clear mode. (15) supply +5 v to v dd and v pp pins. (16) turn off the power for this device. the procedures from (2) to (12) are illustrated in the chart below. data input data output data input gnd v dd + 1 v dd v pp gnd v dd v dd v pp clk d 0 -d 7 md 0 md 1 md 2 md 3 write verify additional write address increment hi-z hi-z hi-z hi-z repeat x times
25 m pd17p068 2.3 prom read procedure data can be read from the prom by using the following procedures. (1) set the pins not used for programming as indicated in section "pin configuration (2) prom programming mode." set the clk pin to low level. (2) supply +5 v to the v dd and v pp pins. (3) provide a 10- m s wait state. (4) program memory address 0 clear mode is entered. (5) supply +6 v to the v dd pin, and +12.5 v to the v pp pin. (6) program inhibit mode is entered. (7) use the verify mode to output data. provide clock pulses to the clk pin to output the data of an address. the address is automatically incremented every four clock pulses. repeat the four-pulse cycles until the last address is reached. (8) program inhibit mode is entered. (9) program memory address 0 clear mode. (10) supply +5 v to the v dd and v pp pins. (11) turn off the power for this device. the procedures from (2) to (9) are illustrated in the chart below. data output gnd v dd v pp gnd v dd + 1 v dd v dd v pp clk d 0 -d 7 md 0 md 1 md 2 hi-z hi-z data output md 3 "l"
26 m pd17p068 3. electrical specifications absolute maximum ratings (t a = 25 ?c) parameter symbol conditions ratings unit supply voltage v dd - 0.3 to +6.0 v input voltage v i - 0.3 to v dd + 0.3 v output voltage v o except for p1a, p2b, p2c - 0.3 to v dd + 0.3 v high-level output current i oh 1 pin - 12 ma all pins - 20 ma low-level output current i ol1 1 pin (except for p1a) 12 ma all pins (except for p1a) 20 ma i ol2 1 pin (p1a only) 17 ma all pins (p1a only) 60 ma output withstand voltage v bds p1a, p2a, p2b, p2c 13 v storage temperature t stg - 55 to +125 ?c caution product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter or even momentarily. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = 25 ?c) parameter symbol conditions min. typ. max. unit supply voltage v dd1 4.5 5.0 5.5 v v dd2 only cpu operates 4.0 5.0 5.5 v v dd3 only watchdog timer operates (cpu stops) 2.3 5.0 5.5 v data retention voltage v ddr clock stops 2.3 5.5 v output withstand voltage v bds p1a, p2a, p2b, p2c 12.5 v supply voltage rise time t rise v dd = 0 ? 4.5 v 3 500 ms input amplitude v in vco 0.7 5.5 v p - p
27 m pd17p068 dc characteristics (reference characteristics: t a = - 40 to +85 ?c, v dd = 5 v 10 %) parameter symbol conditions min. typ. max. unit supply current i dd1 operation of all functions 11 23 ma v dd = 5 v, t a = 25 ?c, f vco = 20 mhz v in = 0.7 v p-p , idc operation osc in = 10 mhz, x in pin square wave input (f in = 8 mhz, v in = v dd ) i dd2 cpu and pll operation 7 12 ma v dd = 5 v, t a = 25 ?c, f vco = 20 mhz v in = 0.7 v p-p , x in pin square wave input (f in = 8 mhz, v in = v dd ) i dd3 only cpu operates 6.5 9 ma v dd = 5 v, t a = 25 ?c, x in pin square wave input (f in = 8 mhz, v in = v dd ) i dd4 halt instruction 2.5 4.5 ma v dd = 5 v, t a = 25 ?c, x in pin square wave input (f in = 8 mhz, v in = v dd ) data retention current i ddr1 main clock stop, watch timer operation 5 10 m a v dd = 2.5 v, t a = 25 ?c main clock stop, watch timer operation 15 25 m a v dd = 5 v, t a = 25 ?c i ddr2 main clock stop, watch timer operation 2 15 m a v dd = 5 v, t a = 25 ?c high-level input voltage v ih1 p0a, p0b, p1b, p1c, p2d 0.7v dd v v ih2 ce, int 0 , int nc , v sync , h sync 0.8v dd v v ih3 p0d 0.7v dd v low-level input voltage v il1 p0a, p0b, p0d, p1b, p1c, p2d 0.2 v dd v v il2 ce, int 0 , int nc , v sync , h sync 0.2 v dd v high-level output current i oh1 p0a 2 , p0a 3 , p0b, p0c, p1b, p1c, p1d, p2d, - 1 - 5ma blank, red, green, blue, psc v oh = v dd - 1 v i oh2 eo v oh = v dd - 1 v - 1 - 2.5 ma low-level output current i ol1 p0a 2 , p0a 3 , p0b, p0c, p1b, p1c, p1d, p2d, 1 10 ma psc v ol = 1 v i ol11 blank, red, green, blue v ol = 1 v 1 8.5 ma i ol2 eo v ol = 1 v 1 6 ma i ol3 p0a 0 , p0a 1 v ol = 1 v 1 4.0 ma i ol4 pwm (p2a, p2b, p2c) v ol = 1 v 1 1.5 ma i ol5 p1a v ol = 1 v 15 30 ma high-level input current i ih vco v ih = v dd 0.1 0.65 1.3 ma high-level output leakage i loh p1a, p2a, p2b, p2c v o = 12.5 v 0.5 m a output off leakage current i l eo v o = v dd or 0 v 10 - 3 1 m a internal pull-down resistor r pd1 p0d (key) v ih = v dd 19 41 85 k w r pd2 p0d (key) v ih = v dd = 5 v 23 41 72 k w r pd3 p0d (key) v ih = v dd = 5 v, t a = 25 ?c 29 41 47 k w
28 m pd17p068 ac characteristics (reference characteristics: t a = - 40 to +85 ?c, v dd = 5 v 10 %) parameter symbol conditions min. typ. max. unit input frequency 1 f vco vco square wave input v in = 0.7 v p - p 0.7 20 mhz input frequency 2 f tmr tmin (p1b 3 ) duty 50 % 45 65 hz input frequency 3 f hs hscnt (p0b 3 ) 10 20 khz a/d converter characteristics (reference characteristics: t a = - 10 to +50 ?c, v dd = 5 v 10 %) parameter symbol conditions min. typ. max. unit a/d conversion absolute accuracy adc 0 -adc 7 1 1.5 lsb a/d conversion resolution adc 0 -adc 7 6 bit a/d input impedance adc 0 -adc 7 1m w dc programming characteristics (t a = 25 ?c, v dd = 6.0 0.25 v, v pp = 12.5 0.5 v) parameter symbol conditions min. typ. max. unit high-level input voltage v ih1 except for clk 0.7 v dd v dd v v ih2 clk v dd - 0.5 v dd v low-level input voltage v il1 except for clk 0 0.3 v dd v v il2 clk 0 0.4 v input leakage current i li v in = v il or v ih 10 m a high-level output voltage v oh i oh = - 1 ma v dd - 1.0 v low-level output voltage v ol i ol = 1 ma 1.0 v v dd supply current i dd 30 ma v pp supply current i pp md 0 = v il , md 1 = v ih 30 ma cautions 1. v pp must not exceed +13.5 v including overshoot. 2. v dd should be applied before v pp and cut after v pp .
29 m pd17p068 ac programming characteristics (t a = 25 ?c, v dd = 6.0 2.5 v, v pp = 12.5 0.5 v) parameter symbol conditions min. typ. max. unit address setup time note (vs. md 0 ? )t as 2 m s md 1 setup time (vs. md 0 ? )t m1s 2 m s data setup time (vs. md 0 ? )t ds 2 m s address hold time note (vs. md 0 )t ah 2 m s data hold time (vs. md 0 )t dh 2 m s md 0 ? data output float delay time t df 0 130 ns v pp setup time (vs. md 3 )t vps 2 m s v dd setup time (vs. md 3 )t vds 2 m s initial program pulse width t pw 0.95 1.0 1.05 ms additional program pulse width t opw 0.95 21.0 ms md 0 setup time (vs. md 1 )t m0s 2 m s md 0 ?? data output delay time t dv md 0 = md 1 = v il 1 m s md 1 hold time (vs. md 0 )t m1h t m1h + t m1r 50 m s2 m s md 1 recovery time (vs. md 0 ? )t m1r 2 m s program counter reset time t pcr 10 m s clk input high-/low-level width t xh, t xl 0.125 m s clk input frequency f x 4.19 mhz initial mode setting time t i 2 m s md 3 setup time (vs. md 1 )t m3s 2 m s md 3 hold time (vs. md 1 ? )t m3h 2 m s md 3 setup time (vs. md 0 ? )t m3sr when program memory is read 2 m s address note ? data output delay time t dad 2 m s address note ? data output hold time t had 0 130 ns md 3 hold time (vs. md 0 )t m3hr 2 m s md 3 ?? data output float delay time t dfr 2 m s note the internal address increment (+1) is performed on the fall of the 3rd clock, where 4 clocks comprise one cycle. the internal clock is not connected to a pin.
30 m pd17p068 program memory write timing program memory read timing gnd gnd clk v dd + 1 v pp v dd v dd md 0 md 1 "l" md 2 md 3 d 0 -d 7 v pp v dd hi-z hi-z t vps t vds t i t dv t dad t xl t xh t had t dfr t m3hr t pcr t m3sr data output data output data input data output data input data input gnd v dd + 1 v pp t vps t vds t i t ds t dh t dv t df v dd v dd d 0 -d 7 md 0 md 1 md 2 md 3 v pp v dd gnd clk t ds t ah t dh t opw t m0s t m1r t m1h t m1s t pcr t pw t m3s t as t xh t xl t m3h hi-z hi-z hi-z hi-z hi-z
31 m pd17p068 4. package drawing 100 pin plastic qfp (14 20) item millimeters inches d f g i j 0.8 0.6 0.65 (t.p.) 0.15 17.2?.2 q 0.677?.008 0.031 0.024 0.006 0.026 (t.p.) s100gf-65-3ba-3 note each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. c 14.0?.2 0.551 m 0.15 0.006 0.125?.075 0.005?.003 +0.004 ?.003 +0.009 ?.008 a 23.2?.2 0.913 h 0.30?.10 0.012 +0.004 ?.005 l 0.8?.2 0.031 +0.009 ?.008 n 0.10 0.004 p 2.7 0.106 s 3.0 max. 0.119 max. +0.10 ?.05 b 20.0?.2 0.787 +0.009 ?.008 +0.009 ?.008 k 1.6?.2 0.063?.008 r5 ? 5 ? m 80 81 50 100 1 31 30 51 n detail of lead end i j f g h q r p k m l a b cd s
32 m pd17p068 appendix development tools the following tools are available to provide m pd17p068s program development environment. hardware product description the ie-17k, ie-17k-et, and emu-17k are in-circuit emulators common to the in-circuit emulator 17k series. the ie-17k and ie-17k-et should be connected with the host computer (pc-9800 series or ibm pc/at tm ) through an rs-232-c cable. the ie-17k emu-17k should be installed to an extension slot in the host computer ie-17k-et note 1 (pc-9800 series). each of the three products function as a dedicated emulator emu-17k note 2 for each device by connecting it with an individual system evaluation board (se board). using simplehost which features an excellent user-machine interface, makes users debugging environment more powerful. if the emu- 17k is used, user can monitor the contents of the data memory in real time. se board this se board is for the m pd17068, 17p068, and 17008. this board can perform evaluations of users system. to debug users programs, use it together with (se-17008) an in-circuit emulator. emulation probe this probe is used when emulating the m pd17p068gf. (ep-17068gf) conversion socket this socket converts pin arrangement for the 100-pin plastic qfp (14 20 mm) to connect the emulation probe ep-17068gf to the target system. (ev-9200gf-100 note 3 ) prom programmer these products write programs to the internal prom of the m pd17p068. to perform programming, the program adapter af-9808l is required to connect af-9703 note 4 to the prom programmer. af-9704 note 4 af-9705 note 4 af-9706 note 4 program adapter this adapter is used together with the prom programmer to program the prom in the m pd17p068. (af-9808l note 4 ) notes 1. inexpensive type: power supply is required to connect externally. 2. manufactured by ic corporation. for details, call 03-3447-3793 tokyo, japan. 3. if the ep-17068gf is purchased, one ev-9200gf-100 is attached as a companion product. ev-9200gf- 100s can separately be purchased in 5-piece units. 4. manufactured by ando electric corporation. for details, call 03-3733-1151 tokyo, japan.
33 m pd17p068 software host product description os media ordering code computer this assembler can be used for all 17k series devices. to develop program of the m pd17p068, the device file (as17068) are also required. this product is the device file for the m pd17p068. pc-9800 series ms-dos this device file is used together with the assembler as17k. ibm pc/at pc dos this software is used to develop programs using an in-circuit emulator and the host computer. this product runs under windows tm system and pro- vides users with an excellent user-machine interface. remark these products run with the versions of the operation systems shown below. os version ms-dos ver.3.30 to ver.5.00a note pc dos ver.3.1 to ver.5.0 note windows ver.3.0 to ver.3.1 note with these products, the task swap function is disabled though the ver.5.00/5.00a of ms-dos and ver.5.0 of the pc dos support the task swap function. 17k series assembler (as17k) device file (as17068) support software ( simplehost ) pc-9800 series ms-dos tm ibm pc/at pc dos tm pc-9800 series ms-dos windows ibm pc/at pc dos 5 inch 2hd m s5a10as17k 3.5 inch 2hd m s5a13as17k 5 inch 2hc m s7b10as17k 3.5 inch 2hc m s7b13as17k 5 inch 2hd m s5a10as17068 3.5 inch 2hd m s5a13as17068 5 inch 2hc m s7b10as17068 3.5 inch 2hc m s7b13as17068 5 inch 2hd m s5a10le17k 3.5 inch 2hd m s5a13le17k 5 inch 2hc m s7b10le17k 3.5 inch 2hc m s7b13le17k
34 m pd17p068 [memo]
35 m pd17p068 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
36 m pd17p068 purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. simplehost is a registered trademark of nec corp. ms-dos and windows are trademarks of microsoft corp. pc/at and pc dos are trademarks of ibm corp. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 94.11

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